Removed caching for RAM: should fix any possible errors because of different cache...

diff --git a/kernel/src/boot.S b/kernel/src/boot.S
index 596383a99fc8488c9061b6eb9023e449d467e4af..f595ff9f79ae6d853dba5bd415b1a66057be8bc2 100644 (file)
--- a/kernel/src/boot.S
+++ b/kernel/src/boot.S
@@ -191,6 +191,7 @@ _start:
 
        # Setup 64-bit paging:
        mov $PML4T - KERNEL_VMA, %eax
+       or $0x10, %eax # NO CACHE
        mov %eax, %cr3
 
        # Enable PAE paging, and global pages:
@@ -261,6 +262,7 @@ _start:
 
        # Setup new page tables:
        mov $PML4T - KERNEL_VMA, %rax
+       or $0x10, %eax # NO CACHE
        mov %rax, %cr3
 
        # Setup TSS address in GDT

diff --git a/kernel/src/paging.cpp b/kernel/src/paging.cpp
index 13ea990b9348ad90e94242b0ff88a192e46a2bb9..f53bc15e0bee4a3d962ca434ecacac2e2dd61a17 100644 (file)
--- a/kernel/src/paging.cpp
+++ b/kernel/src/paging.cpp
@@ -103,7 +103,7 @@ void os::paging::on_all_pages(const os::paging::PML4T& PML4T, void f(page*, phys
 }
 
 void os::paging::load_pml4t(phys_ptr<PML4T> PML4T) {
-       asm volatile("mov %0, %%cr3" :: "r" (PML4T) : "memory");
+       asm volatile("mov %0, %%cr3" :: "r" (PML4T.get_phys_addr() | 0x10) : "memory"); // 0x10 disables the cache.
 }
 
 os::paging::page_allocator_t os::paging::page_allocator{};