From 815ed956f5f43fa0e9fc1faca332c827d2fb4d43 Mon Sep 17 00:00:00 2001 From: Amelia Coutard Date: Thu, 1 Jun 2023 05:34:51 +0200 Subject: [PATCH] Removed caching for RAM: should fix any possible errors because of different cache rules overlapping. Will make it good eventually --- kernel/src/boot.S | 2 ++ kernel/src/paging.cpp | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/kernel/src/boot.S b/kernel/src/boot.S index 596383a..f595ff9 100644 --- a/kernel/src/boot.S +++ b/kernel/src/boot.S @@ -191,6 +191,7 @@ _start: # Setup 64-bit paging: mov $PML4T - KERNEL_VMA, %eax + or $0x10, %eax # NO CACHE mov %eax, %cr3 # Enable PAE paging, and global pages: @@ -261,6 +262,7 @@ _start: # Setup new page tables: mov $PML4T - KERNEL_VMA, %rax + or $0x10, %eax # NO CACHE mov %rax, %cr3 # Setup TSS address in GDT diff --git a/kernel/src/paging.cpp b/kernel/src/paging.cpp index 13ea990..f53bc15 100644 --- a/kernel/src/paging.cpp +++ b/kernel/src/paging.cpp @@ -103,7 +103,7 @@ void os::paging::on_all_pages(const os::paging::PML4T& PML4T, void f(page*, phys } void os::paging::load_pml4t(phys_ptr PML4T) { - asm volatile("mov %0, %%cr3" :: "r" (PML4T) : "memory"); + asm volatile("mov %0, %%cr3" :: "r" (PML4T.get_phys_addr() | 0x10) : "memory"); // 0x10 disables the cache. } os::paging::page_allocator_t os::paging::page_allocator{}; -- 2.47.0